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The routing algorithm is one of the most important components in designing a network-on-chip (NoC). An effective routing algorithm can cause better performance and throughput, and thus, have less latency, lower power consumption and high reliability. Considering the high scalability in networks and fault occurrence on links, the more the packet reaches the destination (i.e. to cross the number of fewer links), the less the loss of packets and information would be. Accordingly, the proposed algorithm is based on reducing the number of passed links to reach the destination.

This paper presents a high-performance NoC that increases telecommunication network reliability by passing fewer links to destination. A large NoC is divided into small districts with central routers. In such a system, routing in large routes is performed through these central routers district by district.

By reducing the number of links, the number of routers also decreases. As a result, the power consumption is reduced, the performance of the NoC is improved, and the probability of collision with a faulty link and network latency is decreased.

The simulation is performed using the Noxim simulator because of its ability to manage and inject faults. The proposed algorithm, XY routing, as a conventional algorithm for the NoC, was simulated in a 14 × 14 network size, as the typical network size in the recent works.

The purpose of this paper is to investigate a more robust ring oscillator. Less sensitivity to power supply variations is a target. This is important since low-quality ring oscillators could be exploited in numerous systems to reduce die costs.

The method in this work is large signal analysis. Delay time as the large signal parameter is calculated symbolically to explore dependency on a power supply voltage. Then simulations are performed to make a comparison. In this work, mathematical justifications are verified via HSPICE circuit simulator outputs, while 0.18 µm TSMC CMOS technology is exploited.

At least two combined configurations are presented with higher robustness. These circuits are more appropriate in noisy conditions. Both theoretical calculations and simulation results verify less sensitive oscillation against supply voltage ripples and temperature variations.

Introducing a band-switched inverter in combined configurations is contribution. In this way, three structures are presented which both show higher stability in oscillation frequency. The band switched delay time calculations are quite new and also the validity of the symbolical delay time approach is verified by circuit simulations.